The number of clock periods shown in this table indicates the time required to perform the operations, store the results and read the next instruction. The number of bus read and write cycles is shown in parenthesis as (r/w). The number of clock periods and the number of read and write cycles must be added respectively to those of the effective address calculation where indicated.
In the following table the headings have the following meanings:
An | = | Address register operand |
Dn | = | Data register operand |
ea | = | An operand specified by an effective address |
M | = | Memory effective address operand |
Standard Instruction Execution Times
Instruction | Size | op<ea>,An ^ | op<ea>,Dn | op Dn,<M> |
ADD | byte,word | 8 ( 1 / 0 ) + | 4 ( 1 / 0 ) + | 8 ( 1 / 1) + |
long | 6 ( 1 / 0 ) + ** | 6 ( 1 / 0 ) + ** | 12 ( 1 / 2) + | |
SUB | byte,word | – | 4 ( 1 / 0 ) + | 8 ( 1 / 1) + |
long | – | 6 ( 1 / 0 ) + ** | 12 ( 1 / 2) + | |
CMP | byte,word | 6 ( 1 / 0 ) + | 4 ( 1 / 0 ) + | – |
long | 6 ( 1 / 0 ) + | 6 ( 1 / 0 ) + | – | |
DIVS | – | – | 158 ( 1 / 0 ) + * | – |
DIVU | – | – | 140 ( 1 / 0 ) + * | – |
EOR | byte,word | – | 4 ( 1 / 0 ) *** | 8 ( 1 / 1 ) + |
long | – | 8 ( 1 / 0 ) *** | 12 ( 1 / 2 ) + | |
– | – | 70 ( 1 / 0 ) + * | – | |
– | – | 70 ( 1 / 0 ) + * | – | |
ADD | byte,word | – | 4 ( 1 / 0 ) + ** | 8 ( 1 / 1 ) + |
long | – | 6 ( 1 / 0 ) + ** | 12 ( 1 / 2) + | |
ADD | byte,word | 8 ( 1 / 0 ) + | 4 ( 1 / 0 ) + | 8 ( 1 / 1 ) + |
long | 6 ( 1 / 0 ) + ** | 6 ( 1 / 0 ) + ** | 12 ( 1 / 2 ) + |
Notes: | + | Add effective address calulation time. | |||||||||
^ | Word or long only. | ||||||||||
* | Indicates maximum value. | ||||||||||
** | The base time of six clock periods is increased to eight if the effective address mode is register direct or immediate (effective address time should also be added). | ||||||||||
*** | Only available effective address mode is data register direct. | ||||||||||
DIVS, DIVU | The divide algorithm used by the MC68000 provides less than 10% difference between the best and the worst case timings. | ||||||||||
MULS, MULU | The multiply algorithm requires 38+2n clocks where n is defined as: | ||||||||||
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