To calculate the timings of most 68000 instructions, you will need to first find the number of cycles used by the addressing mode in the table below (‘Effective Address Operand Calculation Timing‘) and then the timing for the actual instruction in the appropriate table.
Effective Address Operand Calculation Timing
This table lists the number of clock periods required to compute an instruction’s effective address. It includes fetching of any extension words, the address computation , and fetching of the memory operand. The number of bus read and write cycles is shown in parenthesis as (r/w). Note there are no write cycles involved in processing the effective address.
Effective Address Calculation Times
Register | Byte / Word | Long | |
Dn | Data register direct | 0 ( 0 / 0 ) | 0 ( 0 / 0 ) |
An | Address register direct | 0 ( 0 / 0 ) | 0 ( 0 / 0 ) |
Memory | Byte / Word | Long | |
( An ) | Address register indirect | 4 ( 1 / 0 ) | 8 ( 2 / 0 ) |
( An ) + | Address register indirect with postincrement | 4 ( 1 / 0 ) | 8 ( 2 / 0 ) |
– ( An ) | Address register indirect with predecrement | 6 ( 1 / 0 ) | 10 ( 2 / 0 ) |
d ( An ) | Address register indirect with displacement | 8 ( 2 / 0 ) | 12 ( 3 / 0 ) |
d ( An, ix ) | Address register indirect with index | 10 ( 2 / 0 ) | 14 ( 3 / 0 ) |
xxx.W | Absolute short | 8 ( 2 / 0 ) | 12 ( 3 / 0 ) |
xxx.L | Absolute long | 12 ( 3 / 0 ) | 16 ( 4 / 0 ) |
d ( PC ) | Program counter with displancement | 8 ( 2 / 0 ) | 12 ( 3 / 0 ) |
d ( PC, ix ) | Program counter with index | 10 ( 2 / 0 ) | 14 ( 3 / 0 ) |
#xxx | Immidiate | 4 ( 1 / 0 ) | 8 ( 2 / 0 ) |
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