List of registers ordered by address
| Symbol | Description |
|---|---|
| & | Register used by DMA channel only. |
| % | Register used by DMA channel usually, processors sometimes. |
| + | Address register pair. Low word uses DB1-DB15, High word DB0-DB4 |
| ~ | Address not writable by the coprocessor unless COPCON bit 1 is set trueh = new for HiRes chip set. |
| p | New for IAA chip set. |
| A | Agnus/Alice chip set. |
| D | Denise/Lisa chip set. |
| P | Paula chip.W = Write. |
| R | Read only |
| ER | Early read. This is a DMA transfer to RAM, from either the disk or from the blitter. Ram timing requires data to be on the bus earlier thanmicroprocessor read cycles. These transfers are therefore initiated byAgnus timing, rather than a read address on the register address bus(RGA). |
| S | Strobe (Write address with no register bits). |
| PTL/PTH | 20 bit pointer that addresses DMA data. Must be reloaded by aprocessor before use (Vertical blank for bit plane and sprite pointers.and prior to starting the blitter for blitter pointers). (old chips -18 bits). |
| LCL/LCH | 20 bit location (starting address) of DMA data. Used toautomatically restart pointers. such as the Coprocessor program counter(during vertical blank), and the audio sample counter (whenever theaudio lentgh count is finished), (Old chips – 18 bits). |
| MOD | 15 bit Modulo. A number that is automatically added to the memory address at the end of each line to generate the address for thebeginning of the next line. This allows the blitter (or the displaywindow) to operate on (or display) a window of data that is smallerthan the actual picture in memory. (memory map) Uses 15 bits, plussign extended. |
| Name | Address | R/W | Chip’s | Function | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| BLTxDAT | & | ~ | 000 | ER | A | Blitter dest. early read (dummy address) | ||||||||
| DMACONR | ~ | 002 | R | A | P | Dma control (and blitter status) read | ||||||||
| VPOSR | ~ | 004 | R | A | Read vert most sig. bits (and frame flop) | |||||||||
| VHPOSR |
~ | 006 | R | A | Read vert and horiz position of beam | |||||||||
| DSKDATR | ~ | 008 | ER | P | Disk data early read (dummy address) | |||||||||
| JOY0DAT | ~ | 00A | R | D | Joystick-mouse 0 data (Vert, Horiz) | |||||||||
| JOT1DAT |
~ | 00C | R | D | Joystick-mouse 1 data (Vert, Horiz) | |||||||||
| CLXDAT | ~ | 00E | R | D | Collision data reg. (read and clear) | |||||||||
| ADKCONR | ~ | 010 | R | P | Audio,disk control register read | |||||||||
| POT0DAT | ~ | 012 | R | P | Pot counter pair 0 data (Vert, Horiz) | |||||||||
| POT1DAT | ~ | 014 | R | P | Pot counter pair 1 data (Vert, Horiz) | |||||||||
| POTINP | ~ | 016 | R | P | Pot pin data read | |||||||||
| SERDATR | ~ | 018 | R | P | Serial port data and status read | |||||||||
| DSKBYTR | ~ | 01A | R | P | Disk data byte and status read | |||||||||
| INTENA | ~ | 01C | R | P | Interrupt enable bits read | |||||||||
| INTREQR | ~ | 01E | R | P | Interrupt request bits read | |||||||||
| DSKPTH | ~ | 020 | W | A | Disk pointer (high 5 bits) | |||||||||
| DSKPTL | + | ~ | 022 | W | A | Disk pointer (low 15 bits) | ||||||||
| DSKLEN | ~ | 024 | W | P | Disk lentgh | |||||||||
| DSKDAT | & | ~ | 026 | W | P | Disk DMA data write | ||||||||
| REFPTR | & | ~ | 028 | W | A | Refresh pointer | ||||||||
| VPOSW | ~ | 02A | W | A | Write vert most sig. bits(and frame flop) | |||||||||
| VHPOSW | ~ | 02C | W | A | D | Write vert and horiz pos of beam | ||||||||
| COPCON | ~ | 02E | W | A | Coprocessor control reg (CDANG) | |||||||||
| SERDAT | ~ | 030 | W | P | Serial port data and stop bits write | |||||||||
| SERPER | ~ | 032 | W | P | Serial port period and control | |||||||||
| POTGO | ~ | 034 | W | P | Pot count start,pot pin drive enable data | |||||||||
| JOYTEST | ~ | 036 | W | D | Write to all 4 joystick-mouse counters at once | |||||||||
| STREQU | ~ | 038 | S | D | Strobe for horiz sync with VB and EQU | |||||||||
| STRVBL | ~ | 03A | S | D | Strobe for horiz sync with VB (Vert Blank) | |||||||||
| STRHOR | ~ | 03C | S | D | P | Strobe for horizontal sync | ||||||||
| STRLONG | & | ~ | 03E | S | D | Strobe for identification of long horizontal line | ||||||||
| BLTCON0 | ~ | 040 | W | A | Blitter control register 0 | |||||||||
| BLTCON1 | ~ | 042 | W | A | Blitter control register 1 | |||||||||
| BLTAFWM | ~ | 044 | W | A | Blitter first word mask for source A | |||||||||
| BLTALWM | ~ | 046 | W | A | Blitter last word mask for source A | |||||||||
| BLTCPTH | + | ~ | 048 | W | A | Blitter pointer to source C (high 5 bits) | ||||||||
| BLTCPTL | + | ~ | 04A | W | A | Blitter pointer to source C (low 15 bits) | ||||||||
| BLTBPTH | + | ~ | 04C | W | A | Blitter pointer to source B (high 5 bits) | ||||||||
| BLTBPTL | + | ~ | 04E | W | A | Blitter pointer to source B (low 15 bits) | ||||||||
| BLTAPTH | + | ~ | 050 | W | A | Blitter pointer to source A (high 5 bits) | ||||||||
| BLTAPTL | + | ~ | 052 | W | A | Blitter pointer to source A (low 15 bits) | ||||||||
| BPTDPTH | + | ~ | 054 | W | A | Blitter pointer to destn D (high 5 bits) | ||||||||
| BLTDPTL | + | ~ | 056 | W | A | Blitter pointer to destn D (low 15 bits) | ||||||||
| BLTSIZE | ~ | 058 | W | A | Blitter start and size (Windows / Width, Height) | |||||||||
| BLTCON0L | h | ~ | 05A | W | A | Blitter control 0 lower 8 bits (Minterms) | ||||||||
| BLTSIZV | h | ~ | 05C | W | A | Blitter V size (for 15 bit Vert size) | ||||||||
| BLTSIZH | h | ~ | 05E | W | A | Blitter H size & start (for 11 bit Horiz size) | ||||||||
| BLTCMOD | ~ | 060 | W | A | Blitter modulo for source C | |||||||||
| BLTBMOD | ~ | 062 | W | A | Blitter modulo for source B | |||||||||
| BLTAMOD | ~ | 064 | W | A | Blitter modulo for source A | |||||||||
| BLTDMOD | ~ | 066 | W | A | Blitter modulo for destn D | |||||||||
| ~ | 068 | A | ||||||||||||
| ~ | 06A | A | ||||||||||||
| ~ | 06C | A | ||||||||||||
| ~ | 06E | A | ||||||||||||
| BLTCDAT | & | ~ | 070 | W | A | Blitter source C data reg | ||||||||
| BLTBDAT | & | ~ | 072 | W | A | Blitter source B data reg | ||||||||
| BLTADAT | & | ~ | 074 | W | A | Blitter source A data reg | ||||||||
| ~ | 076 | |||||||||||||
| SPRHDAT | ~ | 078 | W | A | Ext logic UHRES sprite pointer and dataidentifier | |||||||||
| BPLHDAT | ~ | 07A | Unknown | |||||||||||
| LISAID | h | ~ | 07C | R | D | Chip revision level for Denise/Lisa | ||||||||
| DSKSYNC | ~ | 07E | W | P | Disk sync pattern reg for disk read | |||||||||
| COP1LCH | + | 080 | W | A | Coprocessor first location reg(high 5 bits) | |||||||||
| COP1LCL | + | 082 | W | A | Coprocessor first location reg(low 15 bits) | |||||||||
| COP2LCH | + | 084 | W | A | Coprocessor second reg(high 5 bits) | |||||||||
| COP2LCL | + | 086 | W | A | Coprocessor second reg(low 15 bits) | |||||||||
| COPJMP1 | 088 | S | A | Coprocessor restart at first location | ||||||||||
| COPJMP2 | 08A | S | A | Coprocessor restart at second location | ||||||||||
| COPINS | 08C | W | A | Coprocessor inst fetch identify | ||||||||||
| DIWSTRT | 08E | W | A | D | Display window start(upper left Vert/Hor pos) | |||||||||
| DIWSTOP | 090 | W | A | D | Display window stop(lower right Vert/Hor pos) | |||||||||
| DDFSTRT | 092 | W | A | Display bit plane data fetch start Horizontal position | ||||||||||
| DDFSTOP | 094 | W | A | Display bit plane data fetch stop Horizontalposition | ||||||||||
| DMACON | 096 | W | A | P | DMA control write (Clear or Set) | |||||||||
| CLXCON | 098 | W | D | Collision control | ||||||||||
| INTENA | 09A | Interrupt enable bits (Clear or Set bits) | ||||||||||||
| INTREQ | 09C | Interrupt request bits (Clear or Set bits) | ||||||||||||
| ADKCON | 09E | W | P | Audio,disk,UART,control | ||||||||||
| AUD0LCH | + | 0A0 | W | A | Audio channel 0 location (High 5 bits) | |||||||||
| AUD0LCL | + | 0A2 | W | A | Audio channel 0 location (Low 15 bits) | |||||||||
| AUD0LEN | 0A4 | W | P | Audio channel 0 lentgh | ||||||||||
| AUD0PER | 0A6 | W | P | Audio channel 0 lentgh | ||||||||||
| AUD0VOL | 0A8 | W | P | |||||||||||
| AUD0DAT | & | 0AA | W | P | ||||||||||
| 0AC | ||||||||||||||
| 0AE | ||||||||||||||
| AUD1LCH | + | 0B0 | W | A | Audio channel 1 location (High 5 bits) | |||||||||
| AUD1LCL | + | 0B2 | W | A | Audio channel 1 location (Low 15 bits) | |||||||||
| AUD1LEN | 0B4 | W | P | Audio channel 1 lentgh | ||||||||||
| AUD1PER | 0B6 | W | P | Audio channel 1 period | ||||||||||
| AUD2VOL | 0B8 | W | P | Audio channel 1 volume | ||||||||||
| AUD2DAT | & | 0BA | W | P | Audio channel 1 data | |||||||||
| 0BC | ||||||||||||||
| 0BE | ||||||||||||||
| AUD2LCH | + | 0C0 | W | A | Audio channel 2 location (High 5 bits) | |||||||||
| AUD2LCL | + | 0C2 | W | A | Audio channel 2 location (Low 15 bits) | |||||||||
| AUD2LEN | 0C4 | W | P | Audio channel 2 lentgh | ||||||||||
| AUD2PER | 0C6 | W | P | Audio channel 2 period | ||||||||||
| AUD2VOL | 0C8 | W | P | Audio channel 2 volume | ||||||||||
| AUD2DAT | & | 0CA | W | P | Audio channel 2 data | |||||||||
| 0CC | ||||||||||||||
| 0CE | ||||||||||||||
| AUD3LCH | + | 0D0 | W | A | Audio channel 3 location (High 5 bits) | |||||||||
| AUD3LCL | + | 0D2 | W | A | Audio channel 3 location (Low 15 bits) | |||||||||
| AUD3LEN | 0D4 | W | P | Audio channel 3 lentgh | ||||||||||
| AUD3PER | 0D6 | W | P | Audio channel 3 period | ||||||||||
| AUD3VOL | 0D8 | W | P | Audio channel 3 volume | ||||||||||
| AUD3DAT | & | 0DA | W | P | Audio channel 3 data | |||||||||
| 0DC | ||||||||||||||
| 0DE | ||||||||||||||
| BPL1PTH | + | 0E0 | W | A | Bit plane pointer 1 (High 5 bits) | |||||||||
| BPL1PTL | + | 0E2 | W | A | Bit plane pointer 1 (Low 15 bits) | |||||||||
| BPL2PTH | + | 0E4 | W | A | Bit plane pointer 2 (High 5 bits) | |||||||||
| BPL2PTL | + | 0E6 | W | A | Bit plane pointer 2 (Low 15 bits) | |||||||||
| BPL3PTH | + | 0E8 | W | A | Bit plane pointer 3 (High 5 bits) | |||||||||
| BPL3PTL | + | 0EA | W | A | Bit plane pointer 3 (Low 15 bits) | |||||||||
| BPL4PTH | + | 0EC | W | A | Bit plane pointer 4 (High 5 bits) | |||||||||
| BPL4PTL | + | 0EE | W | A | Bit plane pointer 4 (Low 15 bits) | |||||||||
| BPL5PTH | + | 0F0 | W | A | Bit plane pointer 5 (High 5 bits) | |||||||||
| BPL5PTL | + | 0F2 | W | A | Bit plane pointer 5 (Low 15 bits) | |||||||||
| BPL6PTH | + | 0F4 | W | A | Bit plane pointer 6 (High 5 bits) | |||||||||
| BPL6PTL | + | 0F6 | W | A | Bit plane pointer 6 (Low 15 bits) | |||||||||
| BPL7PTH | + | 0F8 | W | A | Bit plane pointer 7 (High 5 bits) | |||||||||
| BPL7PTL | + | 0FA | W | A | Bit plane pointer 7 (Low 15 bits) | |||||||||
| BPL8PTH | + | 0FC | W | A | Bit plane pointer 8 (High 5 bits) | |||||||||
| BPL8PTL | + | 0FE | W | A | Bit plane pointer 8 (Low 15 bits) | |||||||||
| BPLCON0 | 100 | W | A | D | Bit plane control register (misc control bits) | |||||||||
| BPLCON1 | 102 | W | D | Bit plane control register (Scroll Val PF1,PF2) | ||||||||||
| BPLCON2 | 104 | W | D | Bit plane control reg (priority control) | ||||||||||
| BPLCON3 | 106 | W | D | Bit plane control reg (enhanced features) | ||||||||||
| BPL1MOD | 106 | W | A | Bit plane modulo (odd planes,or active-fetch lines if bitplane scan-doubling isenabled | ||||||||||
| BPL2MOD | 108 | W | A | Bit plane modulo (even planes or inactive-fetch lines if bitplane scan-doubling isenabled | ||||||||||
| BPLCON4 | p | 10A | W | Bit plane control reg (bitplane and spritemasks) | ||||||||||
| CLXCON2 | p | 10C | W | D | Extended collision control reg | |||||||||
| BPL1DAT | & | 10E | W | D | Bit plane 1 data (parallel to serial convert) | |||||||||
| BPL2DAT | & | 110 | W | D | Bit plane 2 data (parallel to serial convert) | |||||||||
| BPL3DAT | & | 112 | W | D | Bit plane 3 data (parallel to serial convert) | |||||||||
| BPL4DAT | & | 114 | W | D | Bit plane 4 data (parallel to serial convert) | |||||||||
| BPL5DAT | & | 116 | W | D | Bit plane 5 data (parallel to serial convert) | |||||||||
| BPL6DAT | & | 118 | W | D | Bit plane 6 data (parallel to serial convert) | |||||||||
| BPL7DAT | p | & | 11A | W | D | Bit plane 7 data (parallel to serial convert) | ||||||||
| BPL8DAT | p | & | 11E | W | D | Bit plane 8 data (parallel to serial convert) | ||||||||
| SPR0PTH | + | 120 | W | A | Sprite 0 pointer (high 5 bits) | |||||||||
| SPR0PTL | + | 122 | W | A | Sprite 0 pointer (low 15 bits) | |||||||||
| SPR1PTH | + | 124 | W | A | Sprite 1 pointer (high 5 bits) | |||||||||
| SPR1PTL | + | 126 | W | A | Sprite 1 pointer (low 15 bits) | |||||||||
| SPR2PTH | + | 128 | W | A | Sprite 2 pointer (high 5 bits) | |||||||||
| SPR2PTL | + | 12A | W | A | Sprite 2 pointer (low 15 bits) | |||||||||
| SPR3PTH | + | 12C | W | A | Sprite 3 pointer (high 5 bits) | |||||||||
| SPR3PTL | + | 12E | W | A | Sprite 3 pointer (low 15 bits) | |||||||||
| SPR4PTH | + | 130 | W | A | Sprite 4 pointer (high 5 bits) | |||||||||
| SPR4PTL | + | 132 | W | A | Sprite 4 pointer (low 15 bits) | |||||||||
| SPR5PTH | + | 134 | W | A | Sprite 5 pointer (high 5 bits) | |||||||||
| SPR5PTL | + | 136 | W | A | Sprite 5 pointer (low 15 bits) | |||||||||
| SPR6PTH | + | 138 | W | A | Sprite 6 pointer (high 5 bits) | |||||||||
| SPR6PTL | + | 13A | W | A | Sprite 6 pointer (low 15 bits) | |||||||||
| SPR7PTH | + | 13C | W | A | Sprite 7 pointer (high 5 bits) | |||||||||
| SPR7PTL | + | 13E | W | A | Sprite 7 pointer (low 15 bits) | |||||||||
| SPR0POS | % | 140 | W | A | D | Sprite 0 Vert/Horiz start position data | ||||||||
| SPR0CTL | % | 142 | W | A | D | Sprite 0 position and control data | ||||||||
| SPR0DATA | % | 144 | W | D | Sprite 0 image data register A | |||||||||
| SPR0DATB | % | 146 | W | D | Sprite 0 image data register B | |||||||||
| SPR1POS | % | 148 | W | A | D | Sprite 1 Vert/Horiz start position data | ||||||||
| SPR1CTL | % | 14A | W | A | D | Sprite 1 position and control data | ||||||||
| SPR1DATA | % | 14C | W | D | Sprite 1 image data register A | |||||||||
| SPR1DATB | % | 14E | W | D | Sprite 2 image data register B | |||||||||
| SPR2POS | % | 150 | W | A | D | Sprite 2 Vert/Horiz start position data | ||||||||
| SPR2CTL | % | 152 | W | A | D | Sprite 2 position and control data | ||||||||
| SPR2DATA | % | 154 | W | D | Sprite 2 image data register A | |||||||||
| SPR2DATB | % | 156 | W | D | Sprite 2 image data register B | |||||||||
| SPR3POS | % | 158 | W | A | D | Sprite 3 Vert/Horiz start position data | ||||||||
| SPR3CTL | % | 15A | W | A | D | Sprite 3 position and control data | ||||||||
| SPR3DATA | % | 15C | W | D | Sprite 3 image data register A | |||||||||
| SPR3DATB | % | 15E | W | D | Sprite 3 image data register B | |||||||||
| SPR4POS | % | 160 | W | A | D | Sprite 4 Vert/Horiz start position data | ||||||||
| SPR4CTL | % | 162 | W | A | D | Sprite 4 position and control data | ||||||||
| SPR4DATA | % | 164 | W | D | Sprite 4 image data register A | |||||||||
| SPR4DATB | % | 166 | W | D | Sprite 4 image data register B | |||||||||
| SPR5POS | % | 168 | W | A | D | Sprite 5 Vert/Horiz start position data | ||||||||
| SPR5CTL | % | 16A | W | A | D | Sprite 5 position and control data | ||||||||
| SPR5DATA | % | 16C | W | D | Sprite 5 image data register A | |||||||||
| SPR5DATB | % | 16E | W | D | Sprite 5 image data register B | |||||||||
| SPR6POS | % | 170 | W | A | D | Sprite 6 Vert/Horiz start position data | ||||||||
| SPR6CTL | % | 172 | W | A | D | Sprite 6 position and control data | ||||||||
| SPR6DATA | % | 174 | W | D | Sprite 6 image data register A | |||||||||
| SPR6DATB | % | 176 | W | D | Sprite 6 image data register B | |||||||||
| SPR7POS | % | 178 | W | A | D | Sprite 7 Vert/Horiz start position data | ||||||||
| SPR7CTL | % | 17A | W | A | D | Sprite 7 position and control data | ||||||||
| SPR7DATA | % | 17C | W | D | Sprite 7 image data register A | |||||||||
| SPR7DATB | % | 17E | W | D | Sprite 7 image data register B | |||||||||
| COLOR00 | 180 | W | D | Color table 00 | ||||||||||
| COLOR01 | 182 | W | D | Color table 01 | ||||||||||
| COLOR02 | 184 | W | D | Color table 02 | ||||||||||
| COLOR03 | 186 | W | D | Color table 03 | ||||||||||
| COLOR04 | 187 | W | D | Color table 04 | ||||||||||
| COLOR05 | 18A | W | D | Color table 05 | ||||||||||
| COLOR06 | 18C | W | D | Color table 06 | ||||||||||
| COLOR07 | 18E | W | D | Color table 07 | ||||||||||
| COLOR08 | 190 | W | D | Color table 08 | ||||||||||
| COLOR09 | 192 | W | D | Color table 09 | ||||||||||
| COLOR10 | 194 | W | D | Color table 10 | ||||||||||
| COLOR11 | 196 | W | D | Color table 11 | ||||||||||
| COLOR12 | 198 | W | D | Color table 12 | ||||||||||
| COLOR13 | 19A | W | D | Color table 13 | ||||||||||
| COLOR14 | 19C | W | D | Color table 14 | ||||||||||
| COLOR15 | 19E | W | D | Color table 15 | ||||||||||
| COLOR16 | 1A0 | W | D | Color table 16 | ||||||||||
| COLOR17 | 1A2 | W | D | Color table 17 | ||||||||||
| COLOR18 | 1A4 | W | D | Color table 18 | ||||||||||
| COLOR19 | 1A6 | W | D | Color table 19 | ||||||||||
| COLOR20 | 1A8 | W | D | Color table 20 | ||||||||||
| COLOR21 | 1AA | W | D | Color table 21 | ||||||||||
| COLOR22 | 1AC | W | D | Color table 22 | ||||||||||
| COLOR23 | 1AE | W | D | Color table 23 | ||||||||||
| COLOR24 | 1B0 | W | D | Color table 24 | ||||||||||
| COLOR25 | 1B2 | W | D | Color table 25 | ||||||||||
| COLOR26 | 1B4 | W | D | Color table 26 | ||||||||||
| COLOR27 | 1B6 | W | D | Color table 27 | ||||||||||
| COLOR28 | 1B8 | W | D | Color table 28 | ||||||||||
| COLOR29 | 1BA | W | D | Color table 29 | ||||||||||
| COLOR30 | 1BC | W | D | Color table 30 | ||||||||||
| COLOR31 | 1BE | W | D | Color table 31 | ||||||||||
| HTOTAL | h | 1C0 | W | A | Highest number count in horiz line(VARBEAMEN = 1) | |||||||||
| HSSTOP | h | 1C2 | W | A | Horizontal line pos for HSYNC stop | |||||||||
| HBSTRT | h | 1C4 | W | A | D | Horizontal line pos for HBLANK start | ||||||||
| HBSTOP | h | 1C6 | W | A | D | Horizontal line pos for HBLANK stop | ||||||||
| VTOTAL | h | 1C8 | W | A | Highest numbered vertical line(VARBEAMEN = 1) | |||||||||
| VSSTOP | h | 1CA | W | A | Vertical line for VBLANK start | |||||||||
| VBSTRT | h | 1CC | W | A | Vertical line for VBLANK start | |||||||||
| VBSTOP | h | 1CE | W | A | Vertical line for VBLANK stop | |||||||||
| SPRHSTRT | h | 1D0 | W | A | UHRES sprite vertical start | |||||||||
| SPRHSTOP | h | 1D2 | W | A | UHRES sprite vertical stop | |||||||||
| BPLHSTRT | h | 1D4 | W | A | UHRES bit plane vertical stop | |||||||||
| BPLHSTOP | h | 1D6 | W | A | UHRES bit plane vertical stop | |||||||||
| HHPOSW | h | 1D8 | W | A | DUAL mode hires Horizontal beam counter write | |||||||||
| HHPOSR | h | 1DA | W | A | DUAL mode hires Horizontal beam counter read | |||||||||
| BEAMCON0 | h | 1DC | W | A | Beam counter control register(SHRES, UHRES, PAL) | |||||||||
| HSSTRT | h | 1DE | W | A | Horizontal sync start (VARHSY) | |||||||||
| VSSTRT | h | 1E0 | W | A | Vertical sync start (VARVSY) | |||||||||
| HCENTER | h | 1E2 | W | A | Horizontal position for vsync on interlace | |||||||||
| DIWHIGH | h | 1E4 | W | A | D | Display window upper bits for start/stop | ||||||||
| BPLHMOD | h | 1E6 | W | A | UHRES bit plane modulo | |||||||||
| SPRHPTH | h | + | 1E8 | W | A | UHRES sprite pointer (High 5 bits) | ||||||||
| SPRHPTL | h | + | 1EA | W | A | UHRES sprite pointer (Low 15 bits) | ||||||||
| BPLHPTH | h | + | 1EC | W | A | VRam (UHRES) bitplane pointer (High 5 bits) | ||||||||
| BPLHPTL | h | + | 1EE | W | A | VRam (UHRES) bitplane pointer (Low 15 bits) | ||||||||
| 1F0 | Reserved | |||||||||||||
| 1F2 | Reserved | |||||||||||||
| 1F4 | Reserved | |||||||||||||
| 1F6 | Reserved | |||||||||||||
| 1F8 | Reserved | |||||||||||||
| 1FA | Reserved | |||||||||||||
| FMODE | p | 1FC | W | A | D | Fetch mode register | ||||||||
| NO-OP | 1FE | Can also indicate last 2 or 3 refreshcycles or the restart of the COPPER afterlockup. | ||||||||||||
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