New features for AA

32 bit wide data bus supports input of 32-bit wide bitplane data and allows doubling of memory bandwidth. Additional doubling of bandwidth can be achieved by using FAST page mode Ram. The same bandwidth enhancements are available for sprites. Also the maximum number of bitplanes useable in all modes was increased to eight (8).

The color Palette has been expanded to 256 colors deep and 25 bits wide as below

This permits display of 256 simultaneous colors in all resolutions. A palette of 16,777,216 colors are available in all resolutions.

28Mhz clock input allows for cleaner definition of HIRES and SHRES pixels ALICE’S clock genarator is synchronized by means of LISA’s 14MHz and SCLK outputs, Genlock XCLK and XCLKEN pins have been eliminated (external MUX is now required).

A new register bit allows sprites to appear in the screen border regions (BRDRSPRT – See BPLCON3).

A bitplane mask field of 8 bits allows an address offset into the color palette. Two 4-bit mask fields do the same for odd and even sprites.

In Dual Playfield modes,2 4-bitplane playfields are now possible in all resolutions.

Two Extra high-order playfield scrollbits allow seamless scrolling of up to 64 bit wide bitplanes in all resolutions. Resolution of bitplane scroll, display window,and horizontal sprite position has been improved to 35ns in all resolutions.

A new 8-bitplane HAM mode has been created, 6 for colors and 2 for control bits. All HAM modes are available in all resolutions (not just LORES as before).

A RST_input pin has been added, which resets all the bits contained in registers that were new for ECS or LISA: BPLCON, BPLCON, CLXCON, DIWHIG and FMODE

Sprite resolution can be set to LORES,HIRES,SHRES,independant of bitplane resolution.

Attached Sprites are now available in all resolutions.

Hardware Scan Doubling support has been added for bitplanes and sprites. This is intended to allow 15KHz screens to be intelligently displayed on a 31KHz monitor and share the display with 31KHz screens.

Bitplanes

There are now 8 bitplanes instead of 6. In single playfield modes they canaddress 256 colors instead of 64. As long as the memory architecture cansupport the bandwidth, all 8 bitplanes are available in all 3 resolutionsIn the same vein, 4+4 bitplane dualplayfield is available in all 3 resolutions, unless bitplane scan-doubling is enabled, in which case both playfields share the same bitplane modulus register.

Bits 15 thru 8 of BPLCON4 comprise an 8 bit mask for the 8 bitplane address, XOR`ing theindividual bits. This allows the copper to exchange color maps with asingle instruction.

BPLCON1 now contains an 8 bit scroll value for each of the playfields.Granularity of scroll now extends down to 35nSec.(1 SHRES pixel), andscroll can delay playfield thru 32 bus cycles. Bits BPAGEM and BPL32 in new register FMODE control size of bitplane data in BPL1DAT thru BPL8DAT.

The old 6 bitplane HAM mode, unlike before, works in HIRES and SHRESresolutions.As before bitplanes 5 and 6 control it`s function as follows:

There is a new 8 bitplane HAM (Hold and Modify) mode. This mode is invoked when BPU field in BPLCON0 is set to 8 , and HAMEN is set. Bitplanes 1 and 2are used as control bits analagous to the function of bitplanes 5 and 6 in6 bitplane HAM mode:

Since only 6 bitplanes are available for modify data, the data is placed in6 MSB. The 2 LSB are left unmodified, which allows creation of all16,777,216 colors simultaneously, assuming one had a large enough screenand picked one`s base registers judiciously. This HAM mode also works inHIRES and SHRES modes.

For compatibility reasons EHB mode remains intact. Its existence is rathermoot in that we have more than enough colors in the color table to replaceits functionality. As before, EHB is invoked whenever

SHRES = HIRES = HAMEN = DPF = 0 and BPU = 6.

Please note that starting with ECS DENISEthere is a bit in BPLCON2 which disables this mode (KILLEHB).

Bits PF2OF2,1,0 in BPLCON3 determine second playfield`s offset into thecolor table. This is now necessary since playfields in DPF mode can have upto 4 bitplanes. Offset value are as defined in register map.

BSCAN2 bit in FMODE enables bitplane scan-doubling. When V0 bit of DIWSTRTmatches V0 of vertical beam counter, BPL1MOD contains the modulus for thedisplay line, else BPL2MOD is used. When scan-doubled both odd and evenbitplanes use the same modulus on a given line, whereas in normal mode oddbitplanes used BPL1MOD and even bitplanes used BPL2MOD. As a result DualPlayfields screens will probably not display correctly when scan-doubled.

Sprites

Bits SPAGEM and SPR32 in FMODE whether size of sprite load datainSPR0DATA(B) thru SPR7DATA(B) is 16,32, or 64 bits, analagous to bitplanes.BPLCON3 contains several bits relating to sprite behavior. SPRES1 and SPRES0 control sprite resolution, whether they conform to the ECS standardor override to LORES, HIRES or SHRES.

BRDRSPRT, when high,allows sprites tobe visible in border areas. ESPRM7 thru ESPRM4 allow relocation of the evensprite color map. OSPRM7 thru OSPRN4 allow relocation of the odd spritecolor map. In the case of attached sprites OSPRM bits are used.

SSCAN2 bit in FMODE enables sprite scan-doubling. When enabled, individual SH10 bits in SPRxPOS registers control whether or not a given sprite is tobe scan-doubled. When V0 bit of SPRxPOS register matches V0 bit of verticalbeam counter, the given sprite`s DMA is allowed to proceed as before.

If the don`t match, then sprite DMA is disabled and LISA reuses the spritedatafrom the previous line. When sprites are scan-doubled, only the positionand control registers need be modified by the programmer; the dataregisters need no modification.

NOTE: Sprite vertical start and stop positions must be of the same parity,i.e. both odd or even.

Compatibility

RST_pin resets all bits in all registers new to AA. These registers include:BPLCON3, BPLCON4, CLXCON2, DIWHIGH, FMODE.

ECSENA bit (formerly ENBPLCN3) is used to disable those register bits in BPLCON3 that are never accessed by old copper lists, and in addition arerequired by old style copper lists to be in their defaultsettings.Specifically ECSENA forces the following bits to their default lowsettings:

BRDRBLNK, BRDNTRAN, ZDCLKEN, EXTBLKEN, and BRDRSPRT.

CLXCON2 is reset by a write to CLXCON, so that old game programs will beable to correctly detect collisions.

DIWHIGH is reset by writes to DIWSTRT or DIWSTOP. This is interlock isinhertied from ECS Denise.

Genlock

Lots of new genlock features were added to ECS DENISE and arecarried overto LISA. ZDBPEN in BPLCON2 allows any bitplane, selected by ZDBPSEL2,1,0,tobe used as a transparency mask (ZD pin mirrors contents of selectedbitplane).

ZDCTEN disables the old COLOR00 is transparent mode, and allowsthe bit31 position of each color in the color table to controltransparency.ZDCLKEN generates a 14MHz clock synchronized with the videodata that can be used by video post-processors.

Finally, BRDNTRAN in BPLCON3 generates an opaque border region which can be used to frame livevideo.

Color Lookup Table

The color table has grown from 32 13-bit registers to 256 25-bit registers.Several new register bits have been added to BPLCON3 to facilitate loadingthe table with only 32 register addresses. LOCT, selects either the 16 MSBor LSB for loading.

Loading the MSB always loads the LSB as well forcompatibility, so when 24 bit colors are desired load LSB after MSB.BANK2,1,0 of 8 32 address banks for loading as follows:

RDRAM bit in BPLCON2 causes LISA to interpret all color table accesses asreads.

Note: There is no longer any need to “scramble” SHRES color table entries.This artifice is no longer required and pepole who bypass ECS graphics library calls to do their own 28MHz graphics are to be pointed at and publicly humiliated.

Collision

A new register CLXCON2 contains 4 new bits. ENBP7 and ENBP6 are the enablebits for bitplanes 7 and 8, respectively. Similarly, MVBP7 and MPBP8 aretheir match value bits. CLXDAT is unchanged.

Horizontal Comparators

All programmable comparators with the exception of VHPOSW have 35nSecresolution.: DIWHIGH, HBSTOP, SPRCTL, BPLCON1. BPLCON1 has additionalhigh-order bits as well.

Note that horizontal bit position representing140nS resolution has been changed to 3rd least significant bit, where before it used to be a field`s LSB, For example, bit 00 in BPLCON1 used tobe named PF1H0 and now it`s called PF1H2.

Coercion of 15KHz to 31KHz

We have added new hardware features to LISA to aid in properly displaying15KHz and 31KHz viewports together on the same 31KHz display.

LISA canglobally set sprite resolution to LORES, HIRES, or SHRES.LISA will ignore SH10 compare bits in SPRxPOS when scan-doubling, therebyallowing ALICE to use these bits individually set scan-doubling.