This table indicates the number of clock periods for the conditional instructions. The number of read and write cycles is shown in parenthesis as (r/w). The number of clock periods and the number of read and write cycles must be added respectively to those of the effective address calculation where indicated.
Conditional Instruction Execution Times
Instruction | Displacement | Branch Taken |
Branch Not taken |
Bcc | byte | 10 ( 2 / 0 ) | 8 ( 1 / 0 ) |
word | 10 ( 2 / 0 ) | 12 ( 1 / 0 ) | |
BRA | byte | 10 ( 2 / 0 ) | – |
word | 10 ( 2 / 0 ) | – | |
BSR | byte | 18 ( 2 / 2 ) | – |
word | 18 ( 2 / 2 ) | – | |
DBcc | CC true | – | 12 ( 2 / 0 ) |
CC false | 10 ( 2 / 0 ) | 14 ( 3 / 0 ) |